The present invention relates to semiconductor devices and a process for producing the same. In particular, the invention relates to static memory semiconductor devices employing FET's (field effect transistors) and a process for producing them.
A memory portion of a static memory semiconductor device consists of a plurality of memory cells, each memory cell being made up of a plurality of MOS FET's. In a static memory cell of this type, the electrode has heretofore been connected to the source region or to the drain region of the MOS FET by using an aluminum wiring. However, since the memory portion occupies a very wide area in a chip in which the static memory semiconductor device is formed, the area occupied by the memory portion must be reduced if it is desired to increase the degree of integration of the semiconductor devices. In an attempt to reduce the area of the memory portion or to reduce the size of the memory cell, therefore, attempts have been made to connect a wiring 8 of polycrystalline silicon directly to the source region or the drain region 7 that is surrounded by a field SiO.sub.2 film 5 and a polycrystalline silicon gate 6, as shown in FIGS. 1 and 2. However, the polycrystalline silicon wiring 8 is composed of a first layer that is formed simultaneously with the polycrystalline silicon gate 6, and is usually doped with phosphorus ions of a high concentration to reduce the resistance. The phosphorus ions are doped simultaneously with the formation of the source region and the drain region. While the phosphorus ions are being doped, the depth of an n.sup.+ -type diffusion layer 7 increases beneath the polycrystalline silicon wiring. Namely, the diffusion layer 7 swells beneath the polycrystalline silicon gate 6 as indicated by a dotted line 10 in FIG. 2, and it becomes difficult to obtain an MOSFET having a desired channel length or a desired shallow source region or drain region. To prevent this defect, a sufficient distance d.sub.1 must be provided between an end portion of the polycrystalline silicon gate 6 and an end portion of the polycrystalline silicon wiring 8. This, however, contradicts the purpose of reducing the size of the cell; the degree of integration of the semiconductor devices is not increased.
Therefore, the inventors of the present invention have developed a method by which the polycrystalline silicon gate 6 and the polycrystalline silicon wiring 8 are formed as shown in FIG. 3, and are covered by an insulating film 9 such as PSG (phosphorus silicate glass).
A portion of the insulating film 9 is then selectively removed by photoetching, and an aluminum wiring 10 is formed in order to connect a semiconductor region 7 to the polycrystalline silicon wiring 8. It was, however, discovered that when the aluminum layer is brought into direct contact with the semiconductor region (source or drain region), there is formed an aluminum-silicon alloy which destroys a pn junction at a depth of as much as about 1 .mu.m in the source or the drain region.